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CY28RS400
Clock Generator for ATI RS400 Chipset
Features
* Supports Intel CPU * Selectable CPU frequencies * Differential CPU clock pairs * 100-MHz differential SRC clocks * 48-MHz USB clock * 33-MHz PCI clock * Low-voltage frequency select input * I2C support with readback capabilities * Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction * 3.3V power supply * 56-pin SSOP and TSSOP packages
CPU x3 SRC x8 PCI x1 REF x3 USB_48 x1
Block Diagram
XIN XOUT CPU_STP# CLKREQ[0:1]# FS_[C:A] VTT_PWRGD# IREF
Pin Configuration
VDD_REF REF[0:2]
XTAL OSC PLL1
PLL Ref Freq
Divider Network
PD
PLL2
SDATA SCLK
I2C Logic
Xin XOUT VDD_48 VDD_CPU USB_48 CPUT[0:2], CPUC[0:2], VSS_48 VDD_SRC VTT_PWRGD#/PD SRCT[0:5],SRCC[0:5] SCLK SDATA VDD_SRCS SRCST[0:1],SRCSC[0:1] FSC CLKREQ#0 VDD_PCI CLKREQ#1 PCI SRCT5 SRCC5 VDD_SRC VSS_SRC VDD_48 MHz SRCT4 SRCC4 SRCT3 USB_48 SRCC3 VSS_SRC VDD_SRC SRCT2 SRCC2 SRCT1 SRCC1 VSS_SRC SRCST1 SRCSC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VDD_REF VSS_REF REF0/FSA REF1/FSB REF2 VDD_PCI PCI0/409_410 VSS_PCI CPU_STOP# CPUT0 CPUC0 VDD_CPU VSS_CPU CPUT1 CPUC1 CPUT2 CPUC2 VDDA VSSA IREF VSS_SRC1 VDD_SRC1 SRCT0 SRCC0 VDD_SRCS VSS_SRCS SRCST0 SRCSC0
56 SSOP/TSSOP
CY28RS400
Cypress Semiconductor Corporation Document #: 38-07637 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised October 19, 2004
CY28RS400
Pin Description
Pin No. 47,46,43,42, 41,40 50 Name CPUT/C[2:0] PCI0/409_410 Type O, DIF Differential CPU clock output. Intel Type-X buffer. I/O, PD 33-MHz clock output/CPU Frequency table Select Intel Type-5 buffer. 0 = 410 frequency select table 1 = 409 frequency select table. This has an internal pull-down A precision resistor attached to this pin is connected to the internal current reference. Description
37 54 53 52 7 8 27, 28, 30, 29 12, 13, 16, 17, 18, 19, 22, 23, 24, 25 ,34,33 10,11
IREF REF0/ FSA REF1/FSB REF2 SCLK SDATA SRCST/C[1:0] SRCT/C[5:0]
I
I/O, SE, 14.318MHz REF clock ouput/ CPU Frequency Select. Intel Type-5 buffer. I/O, SE 14.318MHz REF clock ouput/ CPU Frequency Select. Intel Type-5 buffer. O, SE 14.318MHz REF clock ouput. Intel Type-5 buffer. I,PU SMBus-compatible SCLOCK.This pin has an internal pullup, but is tri-stated in power-down. I/O, PU SMBus compatible SDATA.This pin has an internal pullup, but is tri-stated in power-down. O, DIF Differential Selectable Serial reference clock. Intel Type-X buffer. Includes overclock support through SMBUS O, DIF 100 MHz Differential Serial reference clock. Intel Type-X buffer.
CLKREQ#[0:1]
I, SE, Output Enable control for SRCT/C. Output enable control required by Minicard PD specification. These pins have an internal pull-down. 0 = Selected SRC outputs are enabled, 1 = Selected SRC outputs are disabled O, SE 48-MHz clock output. Intel Type-3A buffer. I PD I, PU I PWR PWR PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND GND GND I O 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B, FS_C and 409_410 inputs. After asserting VTT_PWRGD# (active low), this pin becomes a realtime input for asserting power down (active high) 3.3V LVTTL input. This pin is used to gate the CPU outputs. CPU outputs are turned off two cycles after assertion of this pin 3.3V LVTTL input. CPU Clock Frequency Select 3.3V power supply for USB outputs 3.3V power supply for CPU outputs 3.3V power supply for PCI outputs 3.3V power supply for REF outputs 3.3V power supply for SRC outputs 3.3V power supply for SRC outputs 3.3V power supply for SRCS outputs 3.3V Analog Power for PLLs Ground for USB outputs Ground for CPU outputs Ground for PCI outputs Ground for REF outputs Ground for SRC outputs Ground for SRC outputs Ground for SRCS outputs Analog Ground 14.318-MHz Crystal Input 14.318-MHz Crystal Output
4 6
USB_48 VTT_PWRGD#/PD
48 9 3 45 51 56 14, 21 35 32 39 5 44 49 55 15, 20, 26 36 31 38 1 2
CPU_STP# FSC VDD_48 VDD_CPU VDD_PCI VDD_REF VDD_SRC VDD_SRC1 VDD_SRCS VDDA VSS_48 VSS_CPU VSS_PCI VSS_REF VSS_SRC VSS_SRC1 VSS_SRCS VSSA XIN XOUT
Document #: 38-07637 Rev. *B
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CY28RS400
Frequency Select Pins (FS_A, FS_B, FS_C and 409_410)
Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C and 409_410 inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B, FS_C and 409_410 input values. For all logic levels of FS_A, FS_B, FS_C and 409_410 VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B, FS_C and 409-410 transitions will be ignored. There are 2 CPU frequency select tables. One based on the CK409 specifications and one based on the CK410 specifications. The table to be used is determined by the value latched on the PCI0/409_410 pin by the VTT_PWRGD/PD# pin. A '0' on this pin selects the 410 frequency table and a '1' on this pin selects the 409 frequency table. In the 409 table, only the FS_A and FS_B pins influence the frequency selection.
Table 1. Frequency Select Table (FS_A FS_B FS_C) 410 mode, 409_410 = 0 FS_C 1 0 0 0 1 FS_B 0 0 1 0 1 FS_A 1 1 0 0 1 CPU 100 MHz 133 MHz 200 MHz 266 MHz Reserved SRC 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz PCIF/PCI 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz REF0 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz USB 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz
Table 2. Frequency Select Table (FS_A FS_B) 410 mode, 409_410 = 1 FS_B 0 0 1 FS_A 0 1 0 CPU 100 MHz 133 MHz 200 MHz SRC 100 MHz 100 MHz 100 MHz PCIF/PCI 33 MHz 33 MHz 33 MHz REF0 14.318 MHz 14.318 MHz 14.318 MHz USB 48 MHz 48 MHz 48 MHz
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3. The block write and block read protocol is outlined in Table 4 while Table 5 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description
Table 3. Command Code Definition Bit 7 (6:5) (4:0) Chip select address, set to `00' to access device
0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000'
Table 4. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Description Bit 1 8:2 9 10 18:11 19 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Page 3 of 19 Block Read Protocol Description
Document #: 38-07637 Rev. *B
CY28RS400
Table 4. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 27:20 28 36:29 37 45:38 46 .... .... .... .... Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte /Slave Acknowledges Data Byte N -8 bits Acknowledge from slave Stop Description Bit 20 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... Table 5. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 29 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeated start Slave address - 7 bits Read Acknowledge from slave Data from slave - 8 bits NOT Acknowledge Stop Byte Read Protocol Description Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte Count from slave - 8 bits Acknowledge Data byte 1 from slave - 8 bits Acknowledge Data byte 2 from slave - 8 bits Acknowledge Data bytes from slave / Acknowledge Data Byte N from slave - 8 bits NOT Acknowledge Block Read Protocol Description
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CY28RS400
Control Registers
Byte 0:Control Register 0 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name SRC[T/C]5 SRC[T/C]4 SRC[T/C]3 SRC[T/C]2 SRC[T/C]1 SRC [T/C]0 SRCS[T/C]1 SRCS[T/C]0 SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRCS[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRCS[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Description
Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name REF2 REF1 REF0 PCI0 USB_48 CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 REF2 Output Enable 0 = Disable, 1 = Enable REF1 Output Enable 0 = Disable, 1 = Enable REF0 Output Enable 0 = Disable, 1 = Enable PCI0 Output Enable 0 = Disable, 1 = Enable USB_48MHz Output Enable 0 = Disable, 1 = Enable CPU[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Description
Byte 2: Control Register 2 Bit 7 @Pup 1 Name CPUT/C SRCT/C USB_48 PCI Reserved Reserved CPU SRC Reserved Spread Spectrum Selection `0' = -0.35% `1' = -0.50% 48MHz Output Drive Strength 0 = 1x, 1 = 2x 33MHz Output Drive Strength 0 = 1x, 1 = 2x Reserved Reserved CPU/SRC Spread Spectrum Enable 0 = Spread off, 1 = Spread on Reserved Page 5 of 19 Description
6 5 4 3 2 1
1 1 0 1 0 1
Document #: 38-07637 Rev. *B
CY28RS400
Byte 2: Control Register 2 (continued) Bit 0 @Pup 1 Name Reserved Reserved Description
Byte 3: Control Register 3 Bit 7 @Pup 1 Name CLKREQ# Description CLKREQ# drive mode 0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when stopped CPU pd drive mode 0 = CPU clocks driven when power down, 1 = CPU clocks tri-state SRC pd drive mode 0 = SRC clocks driven when power down, 1 = SRC clocks tri-state CPU_STOP# drive mode 0 = CPU clocks driven , 1 = CPU clocks tri-state Allow control of CPU2 with CPU_STOP# 0 = CPU2 is free running, 1 = CPU2 is stopped with CPU_STOP# Allow control of CPU1 with CPU_STOP# 0 = CPU1 is free running, 1 = CPU1 is stopped with CPU_STOP# Allow control of CPU0 with CPU_STOP# 0 = CPU0 is free running, 1 = CPU0 is stopped with CPU_STOP# Reserved
6 5 4 3 2 1 0
0 1 0 1 1 1 1
CPU SRC CPU CPU2 CPU1 CPU0 Reserved
Byte 4: Control Register 4 Bit 7 @Pup 0 Name SRC[T/C]5 Description SRC[T/C]5 CLKREQ0 control 1 = SRC[T/C]5 stoppable by CLKREQ#0 pin 0 = SRC[T/C]5 free running SRC[T/C]4 CLKREQ#0 control 1 = SRC[T/C]4 stoppable by CLKREQ#0 pin 0 = SRC[T/C]4 free running SRC[T/C]3 CLKREQ#0 control 1 = SRC[T/C]3 stoppable by CLKREQ#0 pin 0 = SRC[T/C]3 free running SRC[T/C]2 CLKREQ#0 control 1 = SRC[T/C]2 stoppable by CLKREQ#0 pin 0 = SRC[T/C]2 free running SRC[T/C]1 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running SRC[T/C]0 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running Reserved Reserved
6
0
SRC[T/C]4
5
0
SRC[T/C]3
4
0
SRC[T/C]2
3
0
SRC[T/C]1
2
0
SRC[T/C]0
1 0
1 1
Reserved Reserved
Byte 5: Control Register 5 Bit 7 @Pup 0 Name SRC[T/C]5 Description SRC[T/C]5 CLKREQ#1 control 1 = SRC[T/C]5 stoppable by CLKREQ#1 pin 0 = SRC[T/C]5 free running SRC[T/C]4 CLKREQ#1 control 1 = SRC[T/C]4 stoppable by CLKREQ#1 pin 0 = SRC[T/C]4 free running
6
0
SRC[T/C]4
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CY28RS400
Byte 5: Control Register 5 (continued) Bit 5 @Pup 0 Name SRC[T/C]3 Description SRC[T/C]3 CLKREQ#1 control 1 = SRC[T/C]3 stoppable by CLKREQ#1 pin 0 = SRC[T/C]3 free running SRC[T/C]2 CLKREQ#1 control 1 = SRC[T/C]2 stoppable by CLKREQ#1 pin 0 = SRC[T/C]2 free running SRC[T/C]1 CLKREQ#1 control 1 = SRC[T/C]1 stoppable by CLKREQ#1 pin 0 = SRC[T/C]1 free running SRC[T/C]0 CLKREQ#1 control 1 = SRC[T/C]1 stoppable by CLKREQ#1 pin 0 = SRC[T/C]1 free running Reserved Reserved
4
0
SRC[T/C]2
3
0
SRC[T/C]1
2
0
SRC[T/C]0
1 0
0 0
Reserved Reserved
Byte 6: Control Register 6 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 HW HW HW HW Name TEST_SEL TEST_MODE REF Reserved 409_410 FS_C FS_B FS_A REF/N or Tri-state Select 1 = REF/N Clock, 0 = Tri-state Test Clock Mode Entry Control 1 = REF/N or Tri-state mode, 0 = Normal operation REF output drive strength. 0 = Low drive, 1 = High drive. Reserved 409_410 reflects the value of the 409_410 pin sampled on power up. 0 = 409_410 was low during VTT_PWRGD# assertion FS_C Reflects the value of the FS_C pin sampled on power up. 0 = FS_C was low during VTT_PWRGD# assertion. FS_B Reflects the value of the FS_B pin sampled on power up. 0 = FS_B was low during VTT_PWRGD# assertion. FS_A Reflects the value of the FS_A pin sampled on power up. 0 = FS_A was low during VTT_PWRGD# assertion. Description
Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description
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CY28RS400
Crystal Recommendations
The CY28RS400 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28RS400 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Table 6. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 35 ppm Stability (max.) 30 ppm Aging (max.) 5 ppm
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL).
The following diagram shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
Figure 1. Crystal Capacitive Clarification
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the
Clock Chip
crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides.
Ci1
Ci2 Pin 3 to 6p
Cs1
X1
X2
Cs2 Trace 2.8pF
XTAL Ce1 Ce2
Trim 33pF
Figure 2. Crystal Loading Example
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CY28RS400
As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) CLe PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual function pin. During initial power up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled low by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active high input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted high, all clocks need to be driven to a low value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) - Assertion When PD is sampled high by two consecutive rising edges of CPUC, all single-ended outputs will be held low on their next high to low transition and differential clocks must held high or Hi-Zd (depending on the state of the control register drive mode bit) on the next diff clock# high to low transition within four clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to `0', the clock output are held with "Diff clock" pin driven high at 2 x Iref, and "Diff clock#" tristate. If the control register PD drive mode bit corresponding to the output of interest is programmed to "1", then both the "Diff clock" and the "Diff clock#" are three-state. Note the example below shows CPUT = 133 MHz and PD drive mode = `1' for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100,133,200 and 266MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 uS after asserting Vtt_PwrGd#. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip's internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Below is an example showing the relationship of clocks coming up.
=
1 ( Ce1 + Cs1 + Ci1 +
1
1 Ce2 + Cs2 + Ci2
)
CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors Ce .....................................................External trim capacitors Cs.............................................. Stray capacitance (terraced) Ci ........................................................... Internal capacitance (lead frame, bond wires etc.) CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors Ce .....................................................External trim capacitors Cs.............................................. Stray capacitance (terraced) Ci ........................................................... Internal capacitance (lead frame, bond wires etc.)
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF
Figure 3. Power-down Assertion Timing Waveform Document #: 38-07637 Rev. *B Page 9 of 19
CY28RS400
Tstable <1.8nS
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF
Tdrive_PWRDN# <300S, >200mV
Figure 4. Power-down Deassertion Timing Waveform CPU_STP# Assertion The CPU_STP# signal is an active low input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped within two-six CPU clock periods after being sampled by two rising edges of the internal CPUC clock. The final states of the stopped CPU signals are
CPU_STP# CPUT CPUC
CPUT = HIGH and CPUC = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to 6 x (Iref), and the CPUC signal will be Hi-Z. When the control register CPU_STP Hi-Z bit corresponding to the output of interest is programmed to `1', the final state of the stopped CPU clock is low (due to external 50 ohm pull-down resistor), both CPUT clock and CPUC clock outputs will not be driven.
Figure 5. CPU_STP# Assertion Waveform CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is 2 - 6 CPU clock cycles.
CPU_STP# CPUT CPUC CPUT Internal CPUC Internal
Tdrive_CPU_STP#,10nS>200mV
Figure 6. CPU_STP# Deassertion Waveform Document #: 38-07637 Rev. *B Page 10 of 19
CY28RS400
1.8mS CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable)
Figure 7. CPU_STP#= Driven, CPU_PD = Driven
1.8mS CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable)
Figure 8. CPU_STP# = Hi-Z, CPU_PD = Hi-Z CLK_REQ[0:1]# Description The CLKREQ#[1:0] signals are active low input used for clean stopping and starting selected SRC outputs. The outputs controlled by CLKREQ#[1:0] are determined by the settings in register bytes 4 and 5. The CLKREQ# signal is a de-bounced signal in that it's state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or de-assertion. (The assertion and de-assertion of this signal is absolutely asynchronous). CLK_REQ[0:1]# De-assertion [Low to High transition] The impact of deasserting the CLKREQ#[1:0] pins is all DIF outputs that are set in the control registers to stoppable via de-assertion of CLKREQ#[1:0] are to be stopped after their next transition. When the control register CLKREQ# drive mode bit is programmed to `0', the final state of all stopped SRC signals is SRCT clock = High and SRCC = Low. There is to be no change to the output drive current values, SRCT will be driven high with a current value equal 6 x Iref,. When the control register CLKREQ# drive mode bit is programmed to `1', the final state of all stopped DIF signals is low, both SRCT clock and SRCC clock outputs will not be driven. CLK_REQ[0:1]# Assertion [High to Low transition] All differential outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the assertion to active outputs is between two-six SRC clock periods (two clocks are shown) with all SRC outputs resuming simultaneously. If the CLKREQ# drive mode bit is programmed to `1' (three-state), the all stopped SRC outputs must be driven high within 10 ns of CLKREQ#[1:0] assertion to a voltage greater than 200 mV.
CLKREQ#X
SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable)
Figure 9. CLK_REQ#[0:1] Assertion/Deassertion Waveform Document #: 38-07637 Rev. *B Page 11 of 19
CY28RS400
FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM
VDD Clock Gen Clock State State 0 Off Off
0.2-0.3mS Delay State 1
W ait for VTT_PW RGD#
Sample Sels State 2 State 3 On
Device is not affected, VTT_PW RGD# is ignored
Clock Outputs Clock VCO
On
Figure 10. VTT_PWRGD# Timing Diagram
S1 S2 VTT_PWRGD# = Low
Delay >0.25mS
VDD_A = 2.0V
Sample Inputs straps
Wait for <1.8ms S0 S3 VDD_A = off
Power Off
Normal Operation
VTT_PWRGD# = toggle
Enable Outputs
Figure 11. Clock Generator Power-up/Run State Diagram
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CY28RS400
Absolute Maximum Conditions
Parameter VDD VDDA VIN TS TA TJ ESDHBM OJC OJA UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Relative to VSS Non Functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - 2000 - - V-0 1 Max. 4.6 4.6 VDD+0.5 +150 70 150 - 20 60 Unit V V VDC C C C V C/W C/W
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter Description 3.3V 5% Condition Min. 3.135 Max. 3.465 Unit V VDD_REF, 3.3V Operating Voltage VDD_CPU, VDD_PCI, VDD_SRC, VDD_48, VIL_FS VIH_FS FS_A,FS_B and FS_C Input Low Voltage FS_A,FS_B and FS_C Input Low Voltage SDATA, SCLK SDATA, SCLK VDD except Pull-ups or Pull downs 0VSS - 0.3 0.7 - 2.2 VSS - 0.3 2.0 -5 - 2.4 -10 3 3 - 0.7*VDD 0 At max load and frequency PD asserted, Outputs driven PD asserted, Outputs Hi-Z - - -
0.35 VDD + 0.5 1.0 - 0.8 VDD + 0.3 5 0.4 10 5 5 7 VDD 0.3*VDD 450 75 2
V V V V V V mA V V uA pF pF nH V V mA mA mA
VILSMBUS Input Low Voltage VIHSMBUS Input High Voltage VIL VIH IIL VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD IPDD IPDT Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage High-Impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power Down Supply Current Power Down Supply Current
AC Electrical Specifications
Parameter Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification 47.5 52.5 % Description Condition Min. Max. Unit
Document #: 38-07637 Rev. *B
Page 13 of 19
CY28RS400
AC Electrical Specifications (continued)
Parameter TPERIOD TR / TF TCCJ LACC CPU at 0.7V TDC TPERIOD TPERIOD TPERIOD TPERIOD TPERIODSS TPERIODSS TPERIODSS TPERIODSS TPERIODAbs TPERIODAbs TPERIODAbs TPERIODAbs TPERIODSSAbs
Description XIN Period XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long-term Accuracy CPUT and CPUC Duty Cycle 100-MHz CPUT and CPUC Period 133-MHz CPUT and CPUC Period 200-MHz CPUT and CPUC Period 266-MHz CPUT and CPUC Period 100-MHz CPUT and CPUC Period, SSC 133-MHz CPUT and CPUC Period, SSC 200-MHz CPUT and CPUC Period, SSC 266-MHz CPUT and CPUC Period, SSC 100-MHz CPUT and CPUC Absolute period 133-MHz CPUT and CPUC Absolute period 200-MHz CPUT and CPUC Absolute period 266-MHz CPUT and CPUC Absolute period 100-MHz CPUT and CPUC Absolute period, SSC 133-MHz CPUT and CPUC Absolute period, SSC 200-MHz CPUT and CPUC Absolute period, SSC 266-MHz CPUT and CPUC Absolute period, SSC CPUT/C Cycle to Cycle Jitter CPUT and CPUC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Any CPU to CPU Clock Skew Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage SRCT and SRCC Duty Cycle 100-MHz SRCT and SRCC Period
Condition When XIN is driven from an external clock source Measured between 0.3VDD and 0.7VDD As an average over 1-s duration Over 150 ms Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF)
Min. 69.841 - - - 45
Max. 71.0 10.0 500 300 55
Unit ns ns ps ppm % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps % ps ps ps mv mv mv V V V % ns
9.997001 10.00300 7.497751 7.502251 4.998500 5.001500 3.748875 3.751125 9.997001 10.05327 7.497751 7.539950 4.998500 5.026634 3.748875 3.769975 9.912001 10.08800 7.412751 7.587251 4.913500 5.086500 3.663875 3.836125 9.912001 10.13827 7.412751 7.624950 4.913500 5.111634 3.663875 3.854975 - 175 - - - 95 700 20 250 250 100 850 - 550 VHIGH + 0.3 - 0.2 55
TPERIODSSAbs
TPERIODSSAbs
TPERIODSSAbs
TCCJ TR / TF TRFM TR TF TSKEW VHIGH VLOW VOX VOVS VUDS VRB SRC TDC TPERIOD
Measured at crossing point Vox Math averages Figure 13 Math averages Figure 13
- 660 -150 250 - -0.3
See Figure 13. Measure SE Measured at crossing point VOX Measured at crossing point VOX
- 45
9.997001 10.00300
Document #: 38-07637 Rev. *B
Page 14 of 19
CY28RS400
AC Electrical Specifications (continued)
Parameter TPERIODSS TPERIODAbs TPERIODSSAbs
Description 100-MHz SRCT and SRCC Period, SSC 100-MHz SRCT and SRCC Absolute Period
Condition Measured at crossing point VOX Measured at crossing point VOX
Min.
Max.
Unit ns ns ns ps ps ps ppm ps % ps ps mv mv mV V V V % ns ns ns ns ns ns V/n s ps % ns ns ns ns V/n s ps % ns ns
9.997001 10.05327 10.12800 9.872001 9.872001 10.17827 - - - 175 - - - 250 250 125 300 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55
100-MHz SRCT and SRCC Absolute Period, SSC Measured at crossing point VOX Any SRCT/C to SRCT/C Clock Skew Any SRCS clock to Any SRCS clock Skew SRCT/C Cycle to Cycle Jitter SRCT/C Long Term Accuracy SRCT and SRCC Rise and Fall Times Rise/Fall Matching Rise TimeVariation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage PCI Duty Cycle Spread Disabled PCI Period Spread Enabled PCI Period, SSC Spread Disabled PCI Period Spread Enabled PCI Period, SSC PCI high time PCI low time PCI rise and fall times PCI Cycle to Cycle Jitter Duty Cycle Period Absolute Period USB high time USB low time Rise and Fall Times Cycle to Cycle Jitter REF Duty Cycle REF Period REF Absolute Period See Figure 13. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Math averages Figure 13 Math averages Figure 13 Measured at crossing point VOX Measured at crossing point Vox Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF)
TSKEW TSKEW TCCJ LACC TR / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB PCI TDC TPERIOD TPERIODSS TPERIODAbs TPERIODSSAbs
660 -150 250 - -0.3 - 45
29.99100 30.00900 29.9910 30.15980 29.49100 30.50900 29.49100 30.65980 12.0 12.0 1.0 - 45 - - 4.0 500 55
THIGH TLOW TR / TF TCCJ USB TDC TPERIOD TPERIODAbs THIGH TLOW TR / TF TCCJ REF TDC TPERIOD TPERIODAbs
20.83125 20.83542 20.48125 21.18542 8.094 7.694 1.0 - 45 69.8203 10.036 9.836 2.0 350 55 69.8622
68.82033 70.86224
Document #: 38-07637 Rev. *B
Page 15 of 19
CY28RS400
AC Electrical Specifications (continued)
Parameter TR / TF TCCJ TSTABLE TSS TSH Description REF Rise and Fall Times REF Cycle to Cycle Jitter Clock Stabilization from Power-up Stopclock Set-up Time Stopclock Hold Time Condition Measured between 0.8V and 2.0V Measurement at 1.5V Min. 0.5 - - 10.0 0 Max. 4.0 1000 1.8 - - Unit V/n s ps ms ns ns
ENABLE/DISABLE and SET-UP
Test and Measurement Set-up
For PCI Single-ended Signals and Reference The following diagram shows the test load configurations for the single-ended PCI, USB, and REF output signals.
12 60
PCI/ USB
Measurement Point
5pF
12
60
Measurement Point
5pF
12
60
Measurement Point
5pF
12
60
REF
12 60
Measurement Point
5pF
Measurement Point
5pF
Figure 12. Single-ended Load Configuration For Differential CPU and SRC Output Signals The following diagram shows the test load configuration for the differential CPU and SRC outputs.
33 100 4 9 .9 33 100 4 9 .9
CPUT SRCT
M e a s u re m e n t P o in t
2pF
CPUC SRCC IR E F
475
M e a s u re m e n t P o in t
2pF
Figure 13. 0.7V Load Configuration
Document #: 38-07637 Rev. *B
Page 16 of 19
CY28RS400
3 .3 V s ig n a l s
-
T DC
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V 0V
TR
TF
Figure 14. Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number Standard Package Type Product Flow
CY28RS400OC CY28RS400OCT CY28RS400ZC CY28RS400ZCT
Lead-free
56-pin SSOP 56-pin SSOP - Tape and Reel 56-pin TSSOP 56-pin TSSOP - Tape and Reel 56-pin SSOP 56-pin SSOP - Tape and Reel 56-pin TSSOP 56-pin TSSOP - Tape and Reel
Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C
CY28RS400OXC CY28RS400OXCT CY28RS400ZXC CY28RS400ZXCT
Package Diagrams
56-Lead Shrunk Small Outline Package O56
.020
28 1
0.395 0.420 0.292 0.299
DIMENSIONS IN INCHES MIN.
MAX.
29
56
0.720 0.730 SEATING PLANE 0.088 0.092 0.095 0.110
GAUGE PLANE
.010
0.005 0.010
0.025 BSC
0.110 0.008 0.0135 0.008 0.016 0-8
0.024 0.040
51-85062-*C
Document #: 38-07637 Rev. *B
Page 17 of 19
CY28RS400
Package Diagrams (continued)
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28 1
DIMENSIONS IN MM[INCHES] MIN. MAX.
7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244]
REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547] 14.097[0.555]
1.100[0.043] MAX.
GAUGE PLANE 0.25[0.010]
0.20[0.008]
0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.051[0.002] 0.152[0.006] SEATING PLANE 0-8
0.508[0.020] 0.762[0.030]
0.170[0.006] 0.279[0.011]
0.100[0.003] 0.200[0.008]
51-85060-*C
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ATI is a registered trademark of ATI Technologies Inc. HyperTransport is a trademark of the HyperTransport Technology Consortium. Intel and Pentium are registered trademarks of Intel Corporation. AMD is a registered trademark of Advanced Micro Devices, Inc. All product and company names mentioned in this document are trademarks of their respective holder.
Document #: 38-07637 Rev. *B
Page 18 of 19
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY28RS400
Document History Page
Document Title: CY28RS400 Clock Generator for ATI RS400 Chipset Document Number: 38-07637 REV. ECN NO. Issue Date Orig. of Change Description of Change
** *A *B
204582 215824 278494
See ECN See ECN See ECN
RGL RGL RGL
New data sheet Minor Change: To post on the external web Changed pins 10 and 11 from internal Pull up to Pull down . Changed polarity of CLKREQ# Added register byte 3 bits [1:3] for CPU Stop control. Removed all 166, 333 and 400-MHz references Changed the USB Rise/Fall times from 1.0 to 0.5V/ns
Document #: 38-07637 Rev. *B
Page 19 of 19

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